The present invention relates to a flash memory which is a nonvolatile memory, more particularly to a flash memory system provided with a management system for appropriately managing a flash memory.
As a storage medium for use in a computer system, a magnetic recording medium such as a hard disc or a floppy disc has been heretofore used. Above all, the hard disc having a large capacity and capable of operating at a high speed can store a large amount of data, and therefore it is positioned as a central storage medium of the system.
However, the manufacturing process of the hard disc is complicated, and it is difficult to realize its miniaturization, weight-saving and cost reduction. Since a structure is moved during the use of the hard disc, a relatively large consumption power is required, and particularly in the case that the hard disc is applied to a portable apparatus or the like, this problem tends to rise.
As the storage medium other than the hard disc, a flash memory is known as a nonvolatile storage element. In the flash memory, a power supply to maintain storage is unnecessary, but the flash memory, for structural reasons thereof, has a finite physical life of about 1010 in terms of a rewriting time. Therefore, in order to use the flash memory relatively safely and stably for a long period of time, an expired storage element and a section in which a defect occurs are detected, and these troubles need to be avoided to store data. Furthermore, in the case of the flash memory, new data cannot be written over a section in which data has already been stored. Therefore, when the new data is to be stored, a stored content must be once erased before the data is written. However, a unit which can be erased is not an individual storage element (=bit) unit, but it is a block unit such as 4 kilobytes or 8 kilobytes. Therefore, generally, after a data portion other than the data to be rewritten is once taken out of the block to be erased, the block is erased, and the data portion needs to be newly added/written again. In consequence, the write processing operation is very complex.
In Japanese Patent Application Laid-open No. 292798/1990, a flash EEPROM system is described for the purpose of enhancing a writing/reading speed to a flash memory and managing defective cells, and the like. In the flash EEPROM system described therein, an access time is intended to be enhanced using a cache memory. However, shortening of the access time dependent on the cache memory is naturally limited, and in order to further enhance the writing/reading speed to the flash memory, an operation speed of the entire flash memory system needs to be enhanced.
Moreover, in the above-described publication, for the management of the defective cells, and the like, a redundant portion is provided with ECC and another information, and the defective cells, and the like are managed only with the information of the redundant portion. However, since the defective cells, and the like are managed only with the redundant portion, the storage capacity of the redundant portion has to be enlarged, which compresses an area to store actual data. Furthermore, since the system manages the defective cells, and the like only with the redundant portion, before reading the actual data, the redundant data is read, and a propriety of data stored in the memory is judged, or recovering, or the like of the data is performed, which remarkably delays the access time.
An object of the present invention is to realize a flash memory system which has little delay in a writing/reading time, can relatively easily perform a writing operation, can operate at a high speed and which can adequately manage defective sectors, and the like.
The above-described object is attained by the following constitutions.
(1) A flash memory system comprising a memory manager for managing data transmission/reception between a host computer and a flash memory,
said memory manager having an address conversion table for converting a logical address given to the flash memory from the host computer and a physical address as an actual address of the flash memory, said address conversion table being defined in accordance with minimum erasing units of the flash memory.
(2) The flash memory system according to the above (1) comprising said memory manager, a bus interface connectable to the host computer, and a flash memory interface for performing a writing/reading to the flash memory,
said memory manager having data relay means for relaying data transmitted to a side of the flash memory from a side of the host computer and data transmitted to the side of the host computer from the side of the flash memory.
(3) The flash memory system according to the above (1) or (2) wherein:
said address conversion table functions so that a logical block address obtained by dividing, into said minimum erasing units, the logical address used when the host computer designates a minimum storage unit on a storage medium may correspond to
a physical block address obtained by dividing said physical address into said minimum erasing units.
(4) The flash memory system according to any one of the above (1) to (3) wherein the conversion of said logical address and said physical address is performed before the writing/reading of data to the flash memory is started.
(5) The flash memory system according to any one of the above (1) to (4) wherein a size of a physical address area of said flash memory is larger than a size of a logical address area.
(6) The flash memory system according to any one of the above (1) to (5) wherein when a trouble occurs in an arbitrary minimum erasing unit corresponding to said logical address area, the minimum erasing unit is replaced with any one of the minimum erasing units of a portion of the physical address area which does not correspond to the logical address area.
(7) The flash memory system according to any one of the above (1) to (6) wherein:
said data relay means further has a block status table,
this block status table has data indicating a state of said each physical block on the flash memory, and
said data indicates at least whether or not the block is good, whether or not a bad sector is present and whether or not the block is used.
(8) The flash memory system according to any one of the above (1) to (7) wherein said address conversion table is formed on RAM by data read from a redundant portion of the flash memory after resetting.
(9) The flash memory system according to the above (7) or (8) wherein said block status table is formed on the RAM by the data read from the redundant portion of the flash memory after the resetting.
(10) A flash memory system comprising a memory manager for managing data transmission/reception between a host computer and a flash memory,
said memory manager setting a size of an area of a logical address in which the flash memory is accessible from said host computer to be smaller than a size of an area of a physical address as an actual address of the flash memory,
said memory manager having a queue ready for use in a surplus area of the physical address area which does not correspond to the logical address area.
(11) The flash memory system according to the above (10) wherein said memory manager treats said physical address area, said logical address area and said queue every block which is divided into a minimum erasing unit of the flash memory.
(12) The flash memory system according to the above (10) or (11) wherein an area of the flash memory corresponding to said queue is in an erased state.
(13) The flash memory system according to any one of the above (10) to (12) wherein when a trouble occurs in an arbitrary block in the physical address area, said memory manager replaces the block with an arbitrary block in said queue.
(14) The flash memory system according to any one of the above (10) to (13) wherein:
when data is written to the flash memory, said memory manager writes new data to a predetermined block in the queue,
said memory manager sets this data as a logical block address of an estimated writing destination, and sets a block of the estimated writing destination as the queue.
(15) The flash memory system according to the above (14) wherein:
in a case where the estimated writing destination block has data other than data to be updated,
after the transfer of a predetermined amount of data from the host computer is completed,
said memory manager transfers the existing data from the estimated writing destination block to the predetermined block in the queue in which the new data is written.
(16) The flash memory system according to any one of the above (10) to (15) wherein:
said memory manager functions so that the physical address area and the logical address area may correspond to the logical block address and a physical block address divided into the minimum erasing unit, and
said memory manager sets a start position of this correspondence relation as an arbitrary position determined every predetermined-times of resets.
(17) The flash memory system according to any one of the above (10) to (16) wherein:
said memory manager writes data of an arbitrary block in the physical address area corresponding to the logical address area to a block of the queue every predetermined times of resets,
said memory manager sets an address of the block of the queue, in which the data is written, as the logical block address of the arbitrary block in the physical address area, and
said memory manager sets the arbitrary block in said physical address area as the queue.
(18) The flash memory system according to any one of the above (10) to (17) comprising, in addition to said memory manager, a bus interface for connecting to the host computer and a flash memory interface for performing a reading/writing operation to the flash memory.
(19) The flash memory system according to any one of the above (10) to (18) wherein said queue is controlled by a pointer.
(20) The flash memory system according to any one of the above (1) to (19) wherein said minimum erasing unit corresponds to 8 or 16 minimum storage units.
(21) The flash memory system according to any one of the above (1) to (20) wherein said minimum storage unit has a size obtained by adding a data length of redundancy to a data length of one sector.
(22) The flash memory system according to any one of the above (1) to (21) wherein a redundant portion of said minimum storage unit has data indicating at least whether or not the block to which the minimum storage unit belongs is good, whether or not a bad sector is present and whether or not the block is used.
(23) The flash memory system according to any one of the above (1) to (22) wherein in said redundant portion, the same data is stored in one block.
(24) The flash memory system according to any one of the above (1) to (23) wherein said data relay means has two buffers for temporarily storing a predetermined length of data, and said data relay means alternately stores data transmitted from the side of the host computer or from the side of the flash memory in the two buffers, and alternately transmits data from the buffer filled with the data to the side of the flash memory or to the side of the host computer.
(25) The flash memory system according to any one of the above (1) to (24) which is an IC chip.
(26) The flash memory system according to any one of the above (1) to (25) which is a card-shaped external storage system.